You find hardware mistakes before they become permanent, and you make the evidence for correctness matter as much as the architecture. In silicon the cost of being wrong is a respin, so the interesting question in this role is always what your testbench cannot see.
Open for applications. Starts at: Custom silicon gate.
We are taking applications for this role now and building the pipeline for it. The stage above is when the work itself is expected to begin, which is something you deserve to know before you apply rather than after. It is context, not a gate.
Where
In the office together five days a week, in one of our garages, and remote-friendly around your family, arranged one person at a time. We hire across the United States 🇺🇸, India 🇮🇳 and the UAE 🇦🇪.
The work
Develop simulation, constrained-random tests, assertions and formal properties. Own coverage closure, reset and clock-domain checks, and adversarial tests of privileged interfaces. Connect each verification claim to the specification and document what has not been proven.
The milestone
In your first 90 days after program activation, deliver a verification plan and regression environment that exposes seeded functional and security defects.
Required
Nice to have
Evidence
Bring experience with hardware verification, formal reasoning or rigorous pre-silicon validation. You should be able to explain vacuous proofs, coverage gaps and the limits of a testbench.
Evidence, not credentials. We are describing work you can point at, in whatever form it exists.
The exercise
Specify properties for a secure command interface and identify assumptions that could hide an access-control defect.
The package
Indicative pay ranges by market and level are on the compensation page. Plan numbers are confirmed in your offer letter.
Apply
One short form. A person reads every application and you hear back either way. You will get your own link to check where things stand, and you can withdraw or delete your application from it at any time, without an account.
