You turn a proven architectural idea into hardware that computes correctly: the digital logic for an accelerator or subsystem we have justified. The justification matters, because we do not build silicon speculatively, and the work starts once the measurement says it is worth it.
Open for applications. Starts at: Custom silicon gate.
We are taking applications for this role now and building the pipeline for it. The stage above is when the work itself is expected to begin, which is something you deserve to know before you apply rather than after. It is context, not a gate.
Where
In the office together five days a week, in one of our garages, and remote-friendly around your family, arranged one person at a time. We hire across the United States 🇺🇸, India 🇮🇳 and the UAE 🇦🇪.
The work
Develop synthesizable RTL, interfaces, control logic and power-aware behavior. Work with verification, compiler and physical-design engineers from the beginning. Track area, frequency and energy against a documented workload and resist optimizing a benchmark that does not represent the product.
The milestone
In your first 90 days after program activation, deliver a verified block prototype with synthesis results and a traceable specification.
Required
Nice to have
Evidence
Bring digital design fundamentals, SystemVerilog or equivalent RTL experience, and strong reasoning about pipelines, resets, clock domains and backpressure.
Evidence, not credentials. We are describing work you can point at, in whatever form it exists.
The exercise
Review a small streaming datapath for correctness under stalls, reset and malformed input before discussing throughput.
The package
Indicative pay ranges by market and level are on the compensation page. Plan numbers are confirmed in your offer letter.
Apply
One short form. A person reads every application and you hear back either way. You will get your own link to check where things stand, and you can withdraw or delete your application from it at any time, without an account.
